Wafer inspection systems are widely used in semiconductor integrated circuit (IC) fabrication to inspect semiconductor wafers for the presence of abnormalities or defects. IC fabrication involves an extensive process comprising of hundreds of process steps such as implantation, deposition, lithography, etching, and polishing. Knowing with certainty that a process step was performed within tolerable limits of excursion is important to maximize production yield. Yield is defined as the ratio of the number of ICs that meet target specifications to the total number of ICs produced. Functional performance tests on ICs are often possible only after the completion of fabrication of ICs. Meanwhile, a problem in a particular process step may propagate to multiple wafers leading to a serious impact on production yield. To mitigate the possibility of having such a serious impact on yield, it is desirable to inspect semiconductor wafers after every significant step in IC fabrication.
Semiconductor fabs maximize production yield by first establishing maximum tolerable defect count after each significant process step. This is followed by continual monitoring of defect count during production using wafer inspection tools. When defect count exceeds predetermined maximum tolerable limits, information about the properties of defects on wafer, such as size and shape, are obtained from optical and electron based wafer inspection tools. The defect properties thus obtained are used to identify and eliminate the root cause of the defects. For example, consider that defect properties point to the occurrence of a particular type of defect (say, type A). With this information, semiconductor fabs proceed to identify suspicious process steps that are likely to produce defect type A. Each suspicious process step may then be closely examined to identify and eliminate the root-cause(s) of defect type A. Information about defects encountered after each significant process step may also be passed on to future process steps so that future process steps could optimize their recipes to account for existing defects. By promptly detecting excursions in defect count and bringing them back to normalcy, the risk of propagation of defects to a large number of wafers can be contained. Mitigating such a risk leads to yield maximization.
In the last few decades, semiconductor ICs have continually improved in performance. Remarkably, they have also become increasingly inexpensive over the same time period. This trend of performance improvement at lower cost has been primarily made possible by two factors: a) technology node shrinking, and b) wafer size expansion. Technology node shrinking refers to the trend of decreasing sizes of components inside an IC. This leads to a reduction of the size of an IC die, and consequently to an increase in the number of ICs fabricated per wafer. Wafer size expansion refers to the trend of increasing diameters of semiconductor wafers. An increase in wafer size for a given die size also results in an increase in the number of ICs fabricated per wafer. By being able to produce increasingly more ICs per wafer, advances in semiconductor fabrication have been able to not only improve performance but also reduce cost.
However, achieving and maintaining high production yield is becoming increasingly challenging with advanced semiconductor fabrication technologies. This is because defect sensitivity of wafer inspection tools have been significantly lagging behind technology node scaling. Over the last decade, while semiconductor technology nodes shrank from 130 nm to 14 nm (over 9× reduction), defect sensitivity of wafer inspection tools improved from 50 nm to 20 nm (2.5× reduction). In other words, semiconductor technology nodes have been shrinking 3.7 times faster than defect sensitivity. This trend is concerning because maximizing yield of ICs is dependent on minimizing defects that are as small as the smallest structures in ICs. Due to the slower rate of improvement in defect sensitivity of wafer inspection tools, an increasing number of yield affecting defects pass through undetected in leading-edge semiconductor fabrication, resulting in a significant reduction in production yield.
Traditional dark-field wafer inspection tools scan a tiny spot (few micrometers wide) of a laser beam through as many as a billion different points to inspect the entire surface of a large (hundreds of millimeters wide) leading-edge semiconductor wafer. Scattered radiation from the spot is collected with a collection optic having a large numerical aperture and a small field of view. Due to the elaborate scanning procedure, traditional wafer inspection tools are inherently slow. This leads to a reduction in the number of wafers that can be inspected in an hour, a metric known as inspection throughput. In an attempt to improve throughput, these tools scan the spot at high speeds by rapidly moving the wafer. However, any increase in throughput obtained by speeding up scanning comes at the price of reduced defect sensitivity. This is because the amount of time the spot spends on a defect decreases with an increase in scanning speed, leading to a reduction in scattered energy from the defect.
Traditional wafer inspection tools suffer from a number of problems: a) reduced defect sensitivity; b) reduced inspection throughput; c) negligible defect recognition capability; d) trade-off between defect sensitivity and inspection throughput; e) reduced field-of view; f) trade-off between field of view and numerical aperture; g) decreased reliability due to high-speed scanning; and h) deformation of wafer due to high-speed scanning.
Accordingly, there is a need for an improved wafer inspection system that can improve defect sensitivity; improve inspection throughput; improve defect recognition capabilities; relax trade-off between defect sensitivity and inspection throughput; increase field of view; relax trade-off between field of view and numerical aperture; improve reliability; and eliminate wafer deformation.